In a conventional patterning process, an optical planarizing layer (OPL) and anti-reflective coating (ARC) are used together to lithographically define an open area. The OPL and ARC, are subsequently removed by plasma etching or reactive ion etching. A metal layer in the open area is then removed by a wet etching technique. However, with this conventional process, it is difficult to control OPL critical dimension (CD) and profile at the critical block level. An undesirably long over-etch, e.g. 30% or more, is necessary to completely remove the OPL at bottoms of the recesses. Any remaining OPL residue at the bottoms of the recesses will block or prevent the wet etching underneath the residual OPL, such as an underlying metal layer. Moreover, there is risk of damaging the channels with an aggressive over-etching, and the OPL profile and CD control become extremely difficult with a long over-etch process.
FIG. 1A illustrates a top view showing the relative positions of fins 101, dielectric layer 103, and recesses 105 from the cross sectional view of FIG. 1B showing a conventional etch process portion of a fabrication process of a semiconductor device. As shown in FIG. 1A, fins 101 are separated by a dielectric layer 103, and recesses 105 are formed in the dielectric layer 103 on each side of each fin 101. Each of the recesses 105 is intended for a replacement metal gate (not shown) to be formed therein. As illustrated in FIG. 1B, sidewall spacers 107 are formed on each side of each recess 105. A high-k dielectric liner 109 is formed in each recess 105 and on a top surface of each of the fins 101, and a metal liner 111 is formed over the high-k dielectric layer 109. After the OPL and ARC (not shown for illustrative convenience) are removed by plasma etching or reactive ion etching, the metal liner in some of the gate recesses 105 is removed by a wet etching technique. However, the remaining OPL residue 113 at the bottoms of the recesses 105 will undesirably block or prevent the wet etching underneath the residual OPL 113.
Therefore, there is a need in the art for methodology enabling short duration over-etch that leaves no OPL residue in the recess bottoms and concurrently controls OPL CD and profile at the critical block level.